1. Field of the Invention
The present invention relates to methods for modeling and analyzing signal propagation delays through interconnect wires having arbitrary load distributions, and in particular, to such methods which use an interconnect wire model with a network topology which allows an accurate analysis to be performed quickly with numerical analysis methods.
2. Description of the Related Art
Many types of integrated circuits, such as programmable logic devices ("PLDs"), contain many long metal "wires" that are used to carry signals throughout the chip. The point on one of these interconnect wires from which a signal originates is known as a signal "source" and each of the points to which the signal must be propagated is known as a signal "destination." The time it takes for a signal to propagate from its source to one of many possible destinations is known as the "interconnect propagation delay." For a given source and destination, the interconnect propagation delay can vary dramatically depending on the positions of the source and destination, as well as the positions of all other possible destinations for the given source (i.e., the loading on the interconnect wire). For example, some typical propagation delays vary from less than 1 nanosecond to 50 nanoseconds or more.
It is important to be able to accurately predict interconnect propagation delays so as to get an accurate estimate of the speed at which a design will operate. The large range over which interconnect propagation delays can vary makes the task of predicting these delays more difficult than for other internal device delays. Well known techniques such as those used in the SPICE electrical circuit simulator can accurately model (i.e., predict) propagation delays through circuits with up to a few thousand elements, but the computation time required to model these delays using the generalized techniques of time-domain electrical circuit simulation is unacceptably high.